During the manufacture of a semiconductor device comprising memory, several features are commonly formed, such as container capacitors and contacts to underlying conductive features. Methods of formation of these structure often comprise the use of mechanical planarization such as chemical mechanical planarization (CMP).
For example, one method to form a container capacitor bottom plate using CMP is depicted in FIGS. 1-6. FIG. 1 depicts a semiconductor wafer substrate assembly 10 comprising a semiconductor wafer 12 having a plurality of doped source/drain areas 14 which are electrically coupled with a plurality of transistors 16. Each transistor comprises gate oxide 18, a doped polysilicon control gate 20, silicide 22 such as tungsten silicide to increase conductivity of the control gate, and a capping layer 24 of oxide, for example formed using tetraethyl orthosilicate (TEOS). Silicon nitride spacers 26 insulate the control gate 20 and silicide 22 from polysilicon pads 28 to which the container capacitors will be electrically coupled. Further depicted in FIG. 1 is shallow trench isolation (STI, field oxide) 30 which reduces unwanted electrical interaction between adjacent transistors, and a thick layer of deposited oxide 32 such as borophosphosilicate glass (BPSG). A patterned photoresist layer 34 defines the location of the container capacitors to be formed. The FIG. 1 structure may further include other structural elements or differences which, for simplicity of explanation, have not been depicted.
The FIG. 1 structure is subjected to an anisotropic etch which removes the exposed portions of the BPSG layer 32 to form a patterned BPSG layer as depicted in FIG. 2 which provides a base dielectric 32 having a recess for the container capacitor. During this etch, the polysilicon pads 28 and possibly a portion of TEOS capping layer 24 are exposed as depicted in FIG. 2. The remaining photoresist layer 34 is stripped and any polymer (not depicted) which forms during the etch is removed according to means known in the art to provide the FIG. 3 structure.
As depicted in FIG. 4, a conformal conductive layer 40 is formed on the deposited oxide layer 32, and will provide a container capacitor storage node (bottom electrode, bottom capacitor plate) for the completed capacitor. Layer 40 may be a metal layer such at titanium nitride (TiN), a conductive layer comprising metal, or a conductively doped semiconductor. A filler material 42 such as photoresist is formed to fill the containers provided by conductive layer 40. The FIG. 4 structure is then subjected to a planarizing process, such as CMP. This process removes horizontal portions of the photoresist 42, the conductive layer 40, and likely a portion of the BPSG 32 to result in the FIG. 5 structure comprising the container capacitor bottom electrodes 40. The photoresist 42 is removed, for example using an ashing process, and then wafer processing continues to form a completed container capacitor and a functional semiconductor device.
Using CMP to form a structure such as a capacitor bottom plate may result in various problems. For example, complete removal of the conductive layer 40 of FIG. 4 from the upper horizontal portions of layer 32 is required to form discrete bottom electrodes to prevent shorting of the completed capacitors. To ensure electrical isolation between bottom electrodes, an over polish is typically performed. This over polish will decrease the height of the electrode, resulting in decreased capacitance of the completed capacitor. As bottom electrodes are formed at aspect ratios which push processing capabilities, merely forming taller electrodes to compensate for the polishing loss is not desirable.
Further, the formation and removal of resist 42 requires several process steps. For example, after formation of the conductive layer 40 the wafer must be transported from the deposition chamber to a coat track apparatus, where the photoresist is dispensed onto the surface of the spinning wafer, which is then heated to bake out the solvents. The wafer is then transported a CMP apparatus to planarize the surface of the FIG. 4 structure to remove the horizontal portions of the photoresist 42 and the conductive layer 40, then the wafer is cleaned. The wafer is then transported for a manual inspection, and is then again transported to measure the films for process control. After measuring the layers on the wafer, it is transported for a final surface clean to ensure sufficient clearance of conductive layer 40. Finally, the wafer is transported for ashing and removal of the remaining photo resist.
Transporting the wafer for various processing acts associated with the planarization of conductive layer 40, and the processing itself, requires time and material, may result added defects or product loss, and therefore increases device costs. Further, the CMP over polish required to ensure removal of the conductive layer 40 from the upper surface of the dielectric layer may result in decreased capacitance of the completed capacitor by decreasing the overall height of the bottom plate. A method used to form container capacitor storage plates and other features which reduces or eliminates the problems described above would be desirable.